EP2S90F1020C5 Datasheet, PDF (5/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Contents
Contents
Timing Model ....................................................................................................................................... 5–20
Preliminary & Final Timing .......................................................................................................... 5–20
I/O Timing Measurement Methodology .................................................................................... 5–21
Performance .................................................................................................................................... 5–27
Internal Timing Parameters .......................................................................................................... 5–34
Stratix II Clock Timing Parameters .............................................................................................. 5–41
Clock Network Skew Adders ....................................................................................................... 5–50
IOE Programmable Delay ............................................................................................................. 5–51
Default Capacitive Loading of Different I/O Standards .......................................................... 5–52
I/O Delays ....................................................................................................................................... 5–54
Maximum Input & Output Clock Toggle Rate .......................................................................... 5–66
Duty Cycle Distortion ......................................................................................................................... 5–77
DCD Measurement Techniques ................................................................................................... 5–78
High-Speed I/O Specifications .......................................................................................................... 5–87
PLL Timing Specifications .................................................................................................................. 5–91
External Memory Interface Specifications ....................................................................................... 5–94
JTAG Timing Specifications ............................................................................................................... 5–96
Document Revision History ............................................................................................................... 5–97
Chapter 6. Reference & Ordering Information
Software .................................................................................................................................................. 6–1
Device Pin-Outs ..................................................................................................................................... 6–1
Ordering Information ........................................................................................................................... 6–1
Document Revision History ................................................................................................................. 6–2
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