EP2S90F1020C5 Datasheet, PDF (407/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

External Memory Interfaces in Stratix II and Stratix II GX Devices
You can generate C, C#, K, and K# clocks using any of the I/O registers
via the DDR registers. Because of strict skew requirements between K and
K# signals, use adjacent pins to generate the clock pair.
Connect CQ and CQ# pins to the Stratix II or Stratix II GX DQS and DQSn
pins for DLL-based implementations. You must configure DQS and
DQSn as bidirectional pins. However, since CQ and CQ# pins are
output-only pins from the memory, the Stratix II or Stratix II GX device
QDRII SRAM memory interface requires that you ground the DQS and
DQSn output enable. To capture data presented by the memory, connect
the shifted CQ signal to the input latch and connect the active-high input
registers and the shifted CQ# signal is connected to the active-low input
register. For PLL-based implementations, connect QK to the input of the
read PLL and leave QK# unconnected.
Read and Write Operations
Figure 3–5 shows the data and clock relationships in QDRII SRAM
devices at the memory pins during reads. Data is output one-and-a-half
clock cycles after a read command is latched into memory. QDRII SRAM
devices send data within a t_CO time after each rising edge of the read clock
C or C# in multi-clock mode, or the input clock K or K# in single clock
mode. Data is valid until t_DOH time after each rising edge of the read clock
C or C# in multi-clock mode or the input clock K or K# in single clock
mode. The CQ and CQ# clocks are edge-aligned with the read data signal.
These clocks accompany the read data for data capture in Stratix II and
Stratix II GX devices.
Altera Corporation
January 2008
3–11
Stratix II Device Handbook, Volume 2