EP2S90F1020C5 Datasheet, PDF (292/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Hardware Features
where C is the count value set for the counter delay time, (this is the initial
setting in the PLL usage section of the compilation report in the
Quartus II software). If the initial value is 1, C – 1 = 0° phase shift.
Figure 1–14 shows an example of phase shift insertion using the fine
resolution using VCO phase taps method. The eight phases from the VCO
are shown and labeled for reference. For this example, CLK0 is based off
the 0^phase from the VCO and has the C value for the counter set to one.
The CLK1 signal is divided by four, two VCO clocks for high time and two
VCO clocks for low time. CLK1 is based off the 135 phase tap from the
VCO and also has the C value for the counter set to one. The CLK1 signal
is also divided by 4. In this case, the two clocks are offset by 3 _FINE. CLK2
is based off the 0phase from the VCO but has the C value for the counter
set to three. This creates a delay of 2 _COARSE, (two complete VCO
periods).
Figure 1–14. Delay Insertion Using VCO Phase Output and Counter Delay Time
1/8 t_VCO
t_VCO
0
45
90
135
180
225
270
315
CLK0
CLK1
CLK2
t_d0-1
t_d0-2
You can use the coarse and fine phase shifts as described above to
implement clock delays in Stratix II and Stratix II GX devices. The
phase-shift parameters are set in the Quartus II software.
1–28
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009