EP2S90F1020C5 Datasheet, PDF (432/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Stratix II and Stratix II GX DDR Memory Support Overview
For interfaces to DDR SDRAM, DDR2 SDRAM, and RLDRAM II, the
Stratix II or Stratix II GX DDR IOE structure requires you to invert the
incoming DQS signal to ensure proper data transfer. This is not required
for QDRII SRAM interfaces if the CQ signal is wired to the DQS pin and
the CQ# signal is wired to the DQSn pin. The altdq megafunction, by
default, adds the inverter to the inclock port when it generates DQ
blocks. The megafunction also includes an option to remove the inverter
for QDRII SRAM interfaces. As shown in Figure 3–13, the inclock
signal’s rising edge clocks the A_I register, inclock signal’s falling edge
clocks the B_I register, and latch C_I is opened when inclock is 1. In a DDR
memory read operation, the last data coincides with DQS being low. If
you do not invert the DQS pin, you will not get this last data as the latch
does not open until the next rising edge of the DQS signal.
Figure 3–17 shows waveforms of the circuit shown in Figure 3–15.
The first set of waveforms in Figure 3–17 shows the edge-aligned
relationship between the DQ and DQS signals at the Stratix II or
Stratix II GX device pins. The second set of waveforms in Figure 3–17
shows what happens if the shifted DQS signal is not inverted; the last
data, D_n, does not get latched into the logic array as DQS goes to tristate
after the read postamble time. The third set of waveforms in Figure 3–17
shows a proper read operation with the DQS signal inverted after the 90°
shift; the last data, D_n, does get latched. In this case the outputs of register
A_I and latch C_I, which correspond to dataout_h and dataout_l ports,
are now switched because of the DQS inversion. Register A_I, register B_I,
and latch C_I refer to the nomenclature in Figure 3–15.
3–36
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008