EP2S90F1020C5 Datasheet, PDF (497/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
Fast PLL
f
The high-speed differential I/O receiver and transmitter channels use the
fast PLL to generate the parallel global clocks (rx- or tx- clock) and
high-speed clocks (diffioclk). Figure 5–12 shows the locations of the
fast PLLs. The fast PLL VCO operates at the clock frequency of the data
rate. Each fast PLL offers a single serial data rate support, but up to two
separate serialization and/or deserialization factors (from the C0 and C1
fast PLL clock outputs) can be used. Clock switchover and dynamic fast
PLL reconfiguration is available in high-speed differential I/O support
mode.
For additional information on the fast PLL, refer to the PLLs in Stratix II
& Stratix II GX Devices chapter in volume 2 of the Stratix II Handbook or
the PLLs in Stratix II & Stratix II GX Devices chapter in volume 2 of the
Stratix II GX Handbook.
Figure 5–12 shows a block diagram of the fast PLL in high-speed
differential I/O support mode.
Figure 5–12. Fast PLL Block Diagram
Global or
regional clock (2)
Clock (1)
Switchover
Circuitry
Clock
4
÷n
Input
Global or
regional clock (2)
Shaded Portions of the
PLL are Reconfigurable
Phase
Frequency
Detector
PFD
Charge
Pump
VCO Phase Selection
Selectable at each PLL
Output Port
Post-Scale
Counters
÷c0
(5) ₈
Loop
Filter
VCO
÷k
÷c1
÷c2
4
÷c3
÷m
diffioclk0 (3)
loaden0 (4)
diffioclk1 (3)
loaden1 (4)
4
Global clocks
8
Regional clocks
8
to DPA block
Notes to Figure 5–12:
(1) Stratix II fast PLLs only support manual clock switchover.
(2) The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block provided the clock control block is fed by an output from another
PLL or pin-driven dedicated global or regional clock.
(3) In high-speed differential I/O support mode, this high-speed PLL clock feeds the SERDES. Stratix II devices only
support one rate of data transfer per fast PLL in high-speed differential I/O support mode.
(4) This signal is a high-speed differential I/O support SERDES control signal.
(5) If the design enables this ÷2 counter, the device can use a VCO frequency range of 150 to 520 MHz.
Altera Corporation
January 2008
5–13
Stratix II Device Handbook, Volume 2