EP2S90F1020C5 Datasheet, PDF (277/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

PLLs in Stratix II and Stratix II GX Devices
Table 1–6. I/O Standards Supported for Enhanced PLL Pins (Part 2 of 2)
Note (1)
I/O Standard
Differential SSTL-2 Class I
Differential SSTL-2 Class II
Differential SSTL-18 Class I
Differential SSTL-18 Class II
1.8-V differential HSTL Class I
1.8-V differential HSTL Class II
1.5-V differential HSTL Class I
1.5-V differential HSTL Class II
LVDS
HyperTransport technology
Differential LVPECL
Input
INCLK
FBIN
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Output
EXTCLK
v
v
v
v
v
v
v
v
v
v
Note to Table 1–6:
(1) The enhanced PLL external clock output bank does not allow a mixture of both
single-ended and differential I/O standards.
Table 1–7 shows the physical pins and their purpose for the Stratix II and
Stratix II GX enhanced PLLs. For inclk port connections to pins see
“Clock Control Block” on page 1–86.
Table 1–7. Stratix II and Stratix II GX Enhanced PLL Pins (Part 1 of 3) Note (1)
Pin
CLK4p/n
CLK5p/n
CLK6p/n
CLK7p/n
CLK12p/n
CLK13p/n
CLK14p/n
CLK15p/n
PLL5_FBp/n
Description
Single-ended or differential pins that can drive the inclk port for PLLs 6 or 12.
Single-ended or differential pins that can drive the inclk port for PLLs 6 or 12.
Single-ended or differential pins that can drive the inclk port for PLLs 6 or 12.
Single-ended or differential pins that can drive the inclk port for PLLs 6 or 12.
Single-ended or differential pins that can drive the inclk port for PLLs 5 or 11.
Single-ended or differential pins that can drive the inclk port for PLLs 5 or 11.
Single-ended or differential pins that can drive the inclk port for PLLs 5 or 11.
Single-ended or differential pins that can drive the inclk port for PLLs 5 or 11.
Single-ended or differential pins that can drive the fbin port for PLL 5.
Altera Corporation
July 2009
1–13
Stratix II Device Handbook, Volume 2