EP2S90F1020C5 Datasheet, PDF (586/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Active Serial Configuration (Serial Configuration Devices)
Figure 7–11 shows the timing waveform for the FPP configuration
scheme using an enhanced configuration device.
Figure 7–11. Stratix II and Stratix II GX FPP Configuration Using an Enhanced Configuration Device Timing
Waveform
nINIT_CONF or
VCC/nCONFIG ^tLOE
OE/nSTATUS
nCS/CONF_DONE
t_CE
t_HC
t_LC
DCLK
DATA[7..0]
User I/O
Driven High
t_OE
byte byte
1
2
Tri-State
INIT_DONE
byte
n
Tri-State
User Mode
t_CD2UM (1)
Note to Figure 7–11:
(1) The initialization clock can come from the Stratix II or Stratix II GX device’s internal oscillator or the CLKUSR pin.
f
f
For timing information, refer to the Enhanced Configuration Devices
(EPC4, EPC8 & EPC16) Data Sheet in volume 2 of the Configuration
Handbook.
Device configuration options and how to create configuration files are
discussed further in the Software Settings section in volume 2 of the
Configuration Handbook.
Active Serial
Configuration
(Serial
Configuration
Devices)
In the AS configuration scheme, Stratix II and Stratix II GX devices are
configured using a serial configuration device. These configuration
devices are low-cost devices with non-volatile memory that feature a
simple four-pin interface and a small form factor. These features make
serial configuration devices an ideal low-cost configuration solution.
Note that AS mode is only applicable for 3.3-V configurations. If I/O
bank 3 is less than 3.3 V, level shifters are required on the output pins
(DCLK, nCSO, ASDO) from the Stratix II or Stratix II GX device back to the
EPCS device.
1 If VCCIO in bank 3 is set to 1.8 V, an external voltage level
translator is needed to meet the V_IH of the EPCS device (3.3 V).
7–34
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008