EP2S90F1020C5 Datasheet, PDF (321/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Figure 1–35. V_CCINT Plane Partitioned for V_CCA Island
PLLs in Stratix II and Stratix II GX Devices
Thick V_CCA Trace
Because of board constraints, you may not be able to partition a V_CCA
island. Instead, run a thick trace from the power supply to each V_CCA pin.
The traces should be at least 20 mils thick.
In each of these three cases, you should filter each VCCA_PLL pin with a
decoupling circuit, as shown in Figure 1–36. Place a ferrite bead that
exhibits high impedance at frequencies of 50 MHz or higher and a 10-F
tantalum parallel capacitor where the power enters the board. Decouple
each VCCA_PLL pin with a 0.1-F and 0.001-F parallel combination of
ceramic capacitors located as close as possible to the Stratix II or
Stratix II GX device. You can connect the GNDA_PLL pins directly to the
same ground plane as the device’s digital ground.
Altera Corporation
July 2009
1–57
Stratix II Device Handbook, Volume 2