EP2S90F1020C5 Datasheet, PDF (405/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

External Memory Interfaces in Stratix II and Stratix II GX Devices
connect the D ports to any user I/O pins in I/O banks 3, 4, 7, or 8 for
optimal performance. RLDRAM II also uses active-high data mask, DM,
pins for writes. You can connect DM pins to any of the I/O pins in the
same bank as the DQ pins of the FPGA when interfacing with
RLDRAM II CIO devices to any of the I/O pins in the same bank as the D
pins when interfacing with RLDRAM II SIO devices. There is one DM pin
per RLDRAM II device. You can also use I/O pins in banks 1, 2, 5, or 6 to
interface with RLDRAM II devices. However, these banks do not have
dedicated circuitry and can only support RLDRAM II devices at speeds
up to 200 MHz. RLDRAM II interfaces using these banks are supported
using the 1.8-V HSTL Class I I/O support.
Connect the RLDRAM II device’s read clock pins (QK) to Stratix II or
Stratix II GX DQS pins. Because of software requirements, you must
configure the DQS signals as bidirectional pins. However, since QK pins
are output-only pins from the memory, RLDRAM II memory interfacing
in Stratix II and Stratix II GX devices requires that you ground the DQS
pin output enables. Stratix II and Stratix II GX devices use the shifted QK
signal from the DQS logic block to capture data. You can leave the QK#
signal of the RLDRAM II device unconnected, as DQS and DQSn in
Stratix II and Stratix II GX devices are not differential pins.
RLDRAM II devices also have input clocks (CK and CK#) and write
clocks (DK and DK#).
You can use any of the user I/O pins for commands and addresses.
RLDRAM II also offers QVLD pins to indicate the read data availability.
Connect the QVLD pins to the Stratix II or Stratix II GX DQVLD pins,
listed in the pin table.
1
Because the Quartus II software treats the DQVLD pins like DQ
pins, you should ensure that the DQVLD pin is assigned to the
pin table’s recommended pin.
Read and Write Operations
When reading from the RLDRAM II device, data is sent edge-aligned
with the read clock QK and QK#. When writing to the RLDRAM II device,
data must be center-aligned with the write clock (DK and DK#). The
RLDRAM II interface uses the same scheme as in DDR or DDR2 SDRAM
interfaces, where the dedicated circuitry is used during reads to
center-align the data and the read clock inside the FPGA and the PLL
center-aligns the data and write clock outputs. The data and clock
relationship for reads and writes in RLDRAM II is similar to those in DDR
and DDR2 SDRAM as shown in Figures 3–3 and 3–4.
Altera Corporation
January 2008
3–9
Stratix II Device Handbook, Volume 2