EP2S90F1020C5 Datasheet, PDF (639/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Configuring Stratix II and Stratix II GX Devices
CONF_DONE is high, the software indicates that configuration was
successful. After the configuration bit stream is transmitted serially via
the JTAG TDI port, the TCK port is clocked an additional 299 cycles to
perform device initialization.
Stratix II and Stratix II GX devices have dedicated JTAG pins that always
function as JTAG pins. Not only can you perform JTAG testing on
Stratix II and Stratix II GX devices before and after, but also during
configuration. While other device families do not support JTAG testing
during configuration, Stratix II and Stratix II GX devices support the
bypass, idcode, and sample instructions during configuration without
interrupting configuration. All other JTAG instructions may only be
issued by first interrupting configuration and reprogramming I/O pins
using the CONFIG_IO instruction.
The CONFIG_IO instruction allows I/O buffers to be configured via the
JTAG port and when issued, interrupts configuration. This instruction
allows you to perform board-level testing prior to configuring the
Stratix II or Stratix II GX device or waiting for a configuration device to
complete configuration. Once configuration has been interrupted and
JTAG testing is complete, the part must be reconfigured via JTAG
(PULSE_CONFIG instruction) or by pulsing nCONFIG low.
The chip-wide reset (DEV_CLRn) and chip-wide output enable (DEV_OE)
pins on Stratix II and Stratix II GX devices do not affect JTAG
boundary-scan or programming operations. Toggling these pins does not
affect JTAG operations (other than the usual boundary-scan operation).
When designing a board for JTAG configuration of Stratix II or
Stratix II GX devices, consider the dedicated configuration pins.
Table 7–20 shows how these pins should be connected during JTAG
configuration.
When programming a JTAG device chain, one JTAG-compatible header is
connected to several devices. The number of devices in the JTAG chain is
limited only by the drive capability of the download cable. When four or
more devices are connected in a JTAG chain, Altera recommends
buffering the TCK, TDI, and TMS pins with an on-board buffer.
Altera Corporation
January 2008
7–87
Stratix II Device Handbook, Volume 2