EP2S90F1020C5 Datasheet, PDF (439/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

SII52004-4.6
4. Selectable I/O Standards in
Stratix II and Stratix II GX
Devices
Introduction
This chapter provides guidelines for using industry I/O standards in
Stratix^® II and Stratix II GX devices, including:
■ I/O features
■ I/O standards
■ External memory interfaces
■ I/O banks
■ Design considerations
Stratix II and
Stratix II GX I/O
Features
Stratix II and the Stratix II GX devices contain an abundance of adaptive
logic modules (ALMs), embedded memory, high-bandwidth digital
signal processing (DSP) blocks, and extensive routing resources, all of
which can operate at very high core speed.
Stratix II and Stratix II GX devices I/O structure is designed to ensure
that these internal capabilities are fully utilized. There are numerous I/O
features to assist in high-speed data transfer into and out of the device
including:
■ Single-ended, non-voltage-referenced and voltage-referenced I/O
standards
■ High-speed differential I/O standards featuring
serializer/deserializer (SERDES), dynamic phase alignment (DPA),
capable of 1 gigabit per second (Gbps) performance for low-voltage
differential signaling (LVDS), Hypertransport technology, HSTL,
SSTL, and LVPECL
1
HSTL and SSTL I/O standards are used only for PLL clock
inputs and outputs in differential mode. LVPECL is
supported on clock input and outputs of the top and bottom
I/O banks.
■ Double data rate (DDR) I/O pins
■ Programmable output drive strength for voltage-referenced and
non-voltage-referenced single-ended I/O standards
■ Programmable bus-hold
■ Programmable pull-up resistor
■ Open-drain output
■ On-chip series termination
■ On-chip parallel termination
Altera Corporation
4–1
January 2008