EP2S90F1020C5 Datasheet, PDF (601/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Altera Corporation
January 2008
Configuring Stratix II and Stratix II GX Devices
You also have the flexibility to synchronize initialization of multiple
devices or to delay initialization with the CLKUSR option. The Enable
user-supplied start-up clock (CLKUSR) option can be turned on in the
Quartus II software from the General tab of the Device & Pin Options
dialog box. Supplying a clock on CLKUSR will not affect the configuration
process. After all configuration data has been accepted and CONF_DONE
goes high, CLKUSR will be enabled after the time specified as t_CD2CU. After
this time period elapses, Stratix II and Stratix II GX devices require 299
clock cycles to initialize properly and enter user mode. Stratix II and
Stratix II GX devices support a CLKUSR f_MAX of 100 MHz.
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
The Enable INIT_DONE Output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONE pin is used it will be high due to an external 10-k
pull-up resistor when nCONFIG is low and during the beginning of
configuration. Once the option bit to enable INIT_DONE is programmed
into the device (during the first frame of configuration data), the
INIT_DONE pin will go low. When initialization is complete, the
INIT_DONE pin will be released and pulled high. The MAX II device
must be able to detect this low-to-high transition which signals the device
has entered user mode. When initialization is complete, the device enters
user mode. In user-mode, the user I/O pins will no longer have weak
pull-up resistors and will function as assigned in your design.
To ensure DCLK and DATA0 are not left floating at the end of
configuration, the MAX II device must drive them either high or low,
whichever is convenient on your board. The DATA[0] pin is available as
a user I/O pin after configuration. When the PS scheme is chosen in the
Quartus II software, as a default this I/O pin is tri-stated in user mode
and should be driven by the MAX II device. To change this default option
in the Quartus II software, select the Dual-Purpose Pins tab of the Device
& Pin Options dialog box.
The configuration clock (DCLK) speed must be below the specified
frequency to ensure correct configuration. No maximum DCLK period
exists, which means you can pause configuration by halting DCLK for an
indefinite amount of time.
If an error occurs during configuration, the device drives its nSTATUS pin
low, resetting itself internally. The low signal on the nSTATUS pin also
alerts the MAX II device that there is an error. If the Auto-restart
configuration after error option (available in the Quartus II software
from the General tab of the Device & Pin Options dialog box) is turned
on, the Stratix II or Stratix II GX device releases nSTATUS after a reset
time-out period (maximum of 100 µs). After nSTATUS is released and
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Stratix II Device Handbook, Volume 2