EP2S90F1020C5 Datasheet, PDF (245/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

DC & Switching Characteristics
Table 5–103. Document Revision History (Part 3 of 3)
Date and
Document
Version
January 2005,
v2.0
October 2004,
v1.2
July 2004, v1.1
February 2004,
v1.0
Changes Made
● Updated the “Power Consumption” section.
● Added the “High-Speed I/O Specifications” and
“On-Chip Termination Specifications” sections.
● Removed the ESD Protection Specifications
section.
● Updated Tables 5–3 through 5–13, 5–16 through
5–18, 5–21, 5–35, 5–39, and 5–40.
● Updated tables in “Timing Model” section.
● Added Tables 5–30 and 5–31.
● Updated Table 5–3.
● Updated introduction text in the “PLL Timing
Specifications” section.
● Re-organized chapter.
● Added typical values and C_{O U T F B} to Table 5–32.
● Added undershoot specification to Note (4) for
Tables 5–1 through 5–9.
● Added Note (1) to Tables 5–5 and 5–6.
● Added V_{I D} and V_{I C M} to Table 5–10.
● Added “I/O Timing Measurement Methodology”
section.
● Added Table 5–72.
● Updated Tables 5–1 through 5–2 and Tables 5–24
through 5–29.
Added document to the Stratix II Device Handbook.
Summary of Changes
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Altera Corporation
April 2011
5–99
Stratix II Device Handbook, Volume 1