EP2S90F1020C5 Datasheet, PDF (371/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
In single-port RAM configuration, the outputs can only be in
read-during-write mode, which means that during the write operation,
data written to the RAM flows through to the RAM outputs. When the
output registers are bypassed, the new data is available on the rising edge
of the same clock cycle on which it was written. Refer to “Read-During-
Write Operation at the Same Address” on page 2–33 for more information
about read-during-write mode. Table 2–8 shows the port width
configurations for TriMatrix blocks in single-port mode.
Table 2–8. Stratix II and Stratix II GX Port Width Configurations for M512,
M4K, and M-RAM Blocks (Single-Port Mode)
Port Width
Configurations
M512 Blocks
512 × 1
256 × 2
128 × 4
64 × 8
64 × 9
32 × 16
32 × 18
M4K Blocks
4K × 1
2K × 2
1K × 4
512 × 8
512 × 9
256 × 16
256 × 18
128 × 32
128 × 36
M-RAM Blocks
64K × 8
64K × 9
32K × 16
32K × 18
16K × 32
16K × 36
8K × 64
8K × 72
4K × 128
4K × 144
Figure 2–6 shows timing waveforms for read and write operations in
single-port mode.
Figure 2–6. Stratix II and Stratix II GX Single-Port Timing Waveforms
inclock
wren
address
data (1)
q (synch)
q (asynch)
an-1
an
din-1
din
din-2
din-1
a0
din-1
din
a1
a2
a3
a4
a5
a6
din4
din5
din6
din
dout0
dout1
dout2
dout3
din4
dout0
dout1
dout2 dout3
din4
din5
Note to Figure 2–6:
(1) The crosses in the data waveform during read mean “don’t care.”
Altera Corporation
January 2008
2–11
Stratix II Device Handbook, Volume 2