EP2S90F1020C5 Datasheet, PDF (287/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

PLLs in Stratix II and Stratix II GX Devices
Figure 1–11. Phase Relationship Between PLL Clocks in Normal Mode
Phase Aligned
PLL Reference
Clock at the
Input Pin
PLL Clock at the
Register Clock Port
External PLL Clock Outputs (1)
Note to Figure 1–11:
(1) The external clock output can lead or lag the PLL internal clock signals.
Zero Delay Buffer Mode
In the zero delay buffer mode, the external clock output pin is
phase-aligned with the clock input pin for zero delay through the device.
Figure 1–12 shows an example waveform of the PLL clocks’ phase
relationship in this mode. When using this mode, Altera requires that you
use the same I/O standard on the input clock, and output clocks. When
using single-ended I/O standards, the inclk port of the PLL must be fed
by the dedicated CLKp input pin.
Altera Corporation
July 2009
1–23
Stratix II Device Handbook, Volume 2