EP2S90F1020C5 Datasheet, PDF (646/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Device Configuration Pins
Table 7–22 describes the dedicated configuration pins, which are required
to be connected properly on your board for successful configuration.
Some of these pins may not be required for your configuration schemes.
Table 7–22. Dedicated Configuration Pins on the Stratix II and Stratix II GX Device (Part 1 of 10)
Pin Name
V_{C C P D}
User Mode
Configuration
Scheme
N/A
All
Pin Type
Power
Description
Dedicated power pin. This pin is used to power
the I/O pre-drivers, the JTAG input pins, and
the configuration input pins that are affected
by the voltage level of VCCSEL.
VCCSEL
This pin must be connected to 3.3-V. V_CCPD
must ramp-up from 0-V to 3.3-V within 100 ms.
If V_CCPD is not ramped up within this specified
time, your Stratix II or Stratix II GX device will
not configure successfully. If your system does
not allow for a V_CCPD ramp-up time of 100 ms
or less, you must hold nCONFIG low until all
power supplies are stable.
N/A
All
Input
Dedicated input that selects which input buffer
is used on the PLL_ENA pin and the
configuration input pins; nCONFIG, DCLK
(when used as an input), nSTATUS (when
used as an input), CONF_DONE (when used
as an input), DEV_OE, DEV_CLRn,
DATA[7..0], RUnLU, nCE, nWS, nRS, CS,
nCS, and CLKUSR. The 3.3-V/2.5-V input
buffer is powered by V_CCPD, while the 1.8-
V/1.5-V input buffer is powered by V_CCIO.
The VCCSEL input buffer has an internal 5-k
pull-down resistor that is always active. The
VCCSEL input buffer is powered by V_CCINT and
must be hardwired to V_CCPD or ground. A logic
high selects the 1.8-V/1.5-V input buffer, and a
logic low selects the 3.3-V/2.5-V input buffer.
For more information, refer to the “VCCSEL
Pin” section.
7–94
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008