EP2S90F1020C5 Datasheet, PDF (531/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Figure 6–6. Rounding and Saturation Bits
18 × 18 Multiplication
1 Sign
Bit
15 Bits
2 LSBs
18
00
1 Sign
Bit
15 Bits
2 LSBs
18
00
DSP Blocks in Stratix II and Stratix II GX Devices
2 Sign
Bits (1)
36
31 Bits
3 LSBs
000
Saturated Output Result
2 Sign
Bits (1)
31 Bits
1 11
3 LSBs
1 110 00
Rounded Output Result
2 Sign
Bits (1)
31 Bits
2 Sign
3 LSBs Bits (1)
15 Bits
18 Bits
000 ⁺ 000000000000000001000000000000000000
19 LSBs
are Ignored
=
00 0 000 000 0 0 000 0 00 0 0
Note to Figure 6–6:
(1) Both sign bits are the same. The design only uses one sign bit, and the other one is ignored.
If the design performs a multiply_accumulate or multiply_add
operation, the multiplier output is input to the
adder/subtractor/accumulator blocks as a 2.31 value, and the three LSBs
are 0.
Altera Corporation
January 2008
6–15
Stratix II Device Handbook, Volume 2