EP2S90F1020C5 Datasheet, PDF (462/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Stratix II and Stratix II GX I/O Banks
Clock I/O Pins
The PLL clock I/O pins consist of clock inputs (INCLK), external feedback
inputs (FBIN), and external clock outputs (EXTCLK). Clock inputs are
located at the left and right I/O banks (banks 1, 2, 5, and 6) to support fast
PLLs, and at the top and bottom I/O banks (banks 3, 4, 7, and 8) to
support enhanced PLLs. Both external clock outputs and external
feedback inputs are located at enhanced PLL external clock output banks
(banks 9, 10, 11, and 12) to support enhanced PLLs. Table 4–3 shows the
PLL clock I/O support in the I/O banks of Stratix II and Stratix II GX
devices.
Table 4–3. I/O Standards Supported for Stratix II and Stratix II GX PLL Pins (Part 1 of 2)
Enhanced PLL (1)
I/O Standard (2)
Input
Output
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
3.3-V PCI
3.3-V PCI-X
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
Differential SSTL-2 Class I
Differential SSTL-2 Class II
Differential SSTL-18 Class I
Differential SSTL-18 Class II
INCLK
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
FBIN
EXTCLK
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Fast PLL
Input
INCLK
v
v
v
v
v
v
v
v
v
v
v
v
v
4–24
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008