EP2S90F1020C5 Datasheet, PDF (256/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Contents
Stratix II Device Handbook, Volume 2
Remote System Upgrade Registers .............................................................................................. 8–15
Remote System Upgrade State Machine ..................................................................................... 8–19
User Watchdog Timer .................................................................................................................... 8–20
Interface Signals between Remote System Upgrade Circuitry and FPGA Logic Array ...... 8–21
Remote System Upgrade Pin Descriptions ................................................................................. 8–23
Quartus II Software Support .............................................................................................................. 8–24
altremote_update Megafunction .................................................................................................. 8–24
Remote System Upgrade Atom .................................................................................................... 8–28
System Design Guidelines .................................................................................................................. 8–28
Remote System Upgrade With Serial Configuration Devices ................................................. 8–29
Remote System Upgrade With a MAX II Device or Microprocessor and Flash Device ...... 8–29
Remote System Upgrade with Enhanced Configuration Devices .......................................... 8–30
Conclusion ............................................................................................................................................ 8–31
Referenced Documents ....................................................................................................................... 8–31
Document Revision History ............................................................................................................... 8–32
Chapter 9. IEEE 1149.1 (JTAG) Boundary-Scan Testing for Stratix II and Stratix II GX
Devices
Introduction ............................................................................................................................................ 9–1
IEEE Std. 1149.1 BST Architecture ...................................................................................................... 9–2
IEEE Std. 1149.1 Boundary-Scan Register .......................................................................................... 9–4
Boundary-Scan Cells of a Stratix II or Stratix II GX Device I/O Pin ........................................ 9–5
IEEE Std. 1149.1 BST Operation Control ............................................................................................ 9–7
SAMPLE/PRELOAD Instruction Mode ..................................................................................... 9–11
Capture Phase ................................................................................................................................. 9–12
Shift and Update Phases ................................................................................................................ 9–12
EXTEST Instruction Mode ............................................................................................................ 9–13
Capture Phase ................................................................................................................................. 9–14
Shift and Update Phases ................................................................................................................ 9–14
BYPASS Instruction Mode ............................................................................................................ 9–15
IDCODE Instruction Mode ........................................................................................................... 9–16
USERCODE Instruction Mode ..................................................................................................... 9–16
CLAMP Instruction Mode ............................................................................................................ 9–17
HIGHZ Instruction Mode ............................................................................................................. 9–17
I/O Voltage Support in JTAG Chain ................................................................................................ 9–17
Using IEEE Std. 1149.1 BST Circuitry ............................................................................................... 9–19
BST for Configured Devices ............................................................................................................... 9–19
Disabling IEEE Std. 1149.1 BST Circuitry ......................................................................................... 9–20
Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing ............................................................... 9–20
Boundary-Scan Description Language (BSDL) Support ................................................................ 9–21
Conclusion ............................................................................................................................................ 9–21
References ............................................................................................................................................. 9–22
Referenced Documents ....................................................................................................................... 9–22
Document Revision History ............................................................................................................... 9–22
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