EP2S90F1020C5 Datasheet, PDF (428/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Stratix II and Stratix II GX DDR Memory Support Overview
Figure 3–13. Bidirectional DDR I/O Path in Stratix II and Stratix II GX Devices
DFF
OE
(2)
DQ
Note (1)
OE Register A_OE (3)
1
OR2
0
(4)
DFF
DQ
datain_l
Logic Array
datain_h
OE Register B_OE (5)
DFF
DQ
0
1
Output Register A_O
DFF
DQ
TRI (6)
I/O Pin (7)
outclock
combout
dataout_h
Output Register B_O
DFF
QD
dataout_l
Latch_TCHLA
Input Register A_I
DFF
neg_reg_out
QD
QD
ENA
inclock
Latch C _I
Input Register B_I (8)
Notes to Figure 3–13:
(1) All control signals can be inverted at the IOE. The signal names used here match with Quartus II software naming
convention.
(2) The OE signal is active low, but the Quartus II software implements this as active high and automatically adds an
inverter before input to the A_OE register during compilation.
(3) The A_OE register generates the enable signal for general-purpose DDR I/O applications.
(4) This select line is to choose whether the OE signal should be delayed by half-a-clock cycle.
(5) The B_OE register generates the delayed enable signal for the write strobes or write clocks for memory interfaces.
(6) The tristate enable is by default active low. You can, however, design it to be active high. The combinational control
path for the tristate is not shown in this diagram.
(7) You can also have combinational output to the I/O pin; this path is not shown in the diagram.
(8) On the top and bottom I/O banks, the clock to this register can be an inverted register A’s clock or a separate clock
(inverted or non-inverted). On the side I/O banks, you can only use the inverted register A’s clock for this port.
3–32
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008