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EP2S90F1020C5 Datasheet, PDF (403/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1 | |||
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External Memory Interfaces in Stratix II and Stratix II GX Devices
Figure 3â3. Example of a 90° Shift on the DQS Signal Notes (1), (2)
DQS pin to
register delay
DQS at
FPGA pin
Preamble
Postamble
DQ at
FPGA pin
DQS at
IOE registers
90Ë degree (3)
DQ at
IOE registers
DQ pin to
register delay
Notes to Figure 3â3:
(1) RLDRAM II and QDRII SRAM memory interfaces do not have preamble and postamble specifications.
(2) DDR2 SDRAM does not support a burst length of two.
(3) The phase shift required for your system should be based on your timing analysis and may not be 90°.
During write operations to a DDR or DDR2 SDRAM device, the FPGA
needs to send the data to the memory center-aligned with respect to the
data strobe. Stratix II and Stratix II GX devices use a PLL to center-align
the data by generating a 0° phase-shifted system clock for the write data
strobes and a â90° phase-shifted write clock for the write data pins for
DDR and DDR2 SDRAM. Figure 3â4 shows an example of the
relationship between the data and data strobe during a burst-of-four
write.
Altera Corporation
January 2008
3â7
Stratix II Device Handbook, Volume 2
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