EP2S90F1020C5 Datasheet, PDF (460/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Stratix II and Stratix II GX I/O Banks
Programmable I/O Standards
Stratix II and Stratix II GX device programmable I/O standards deliver
high-speed and high-performance solutions in many complex design
systems. This section discusses the I/O standard support in the I/O
banks of Stratix II and Stratix II GX devices.
Regular I/O Pins
Most Stratix II and Stratix II GX device pins are multi-function pins.
These pins support regular inputs and outputs as their primary function,
and offer an optional function such as DQS, differential pin-pair, or PLL
external clock outputs. For example, you can configure a multi-function
pin in the enhanced PLL external clock output bank as a PLL external
clock output when it is not used as a regular I/O pin.
1 I/O pins that reside in PLL banks 9 through 12 are powered by
the VCC_PLL<5, 6, 11, or 12>_OUT pins, respectively. The
EP2S60F484, EP2S60F780, EP2S90H484, EP2S90F780, and
EP2S130F780 devices do not support PLLs 11 and 12. Therefore,
any I/O pins that reside in bank 11 are powered by the VCCIO3
pin, and any I/O pins that reside in bank 12 are powered by the
VCCIO8 pin.
Table 4–2 shows the I/O standards supported when a pin is used as a
regular I/O pin in the I/O banks of Stratix II and Stratix II GX devices.
Table 4–2. Stratix II and Stratix II GX Regular I/O Standards Support (Part 1 of 2)
I/O Standard
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
3.3-V PCI
3.3-V PCI-X
SSTL-2 Class I
SSTL-2 Class II
General I/O Bank
Enhanced PLL External
Clock Output Bank (2)
1 2 3 4 5(1) 6(1) 7 8 9 10 11 12
v v v v vvvvv v v v
v v v v vvvvv v v v
v v v v vvvvv v v v
v v v v vvvvv v v v
v v v v vvvvv v v v
vv
vvv v v v
vv
vvv v v v
v v v v vvvvv v v v
v v v v vvvvv v v v
4–22
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008