EP2S90F1020C5 Datasheet, PDF (541/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

DSP Blocks in Stratix II and Stratix II GX Devices
The 36-bit multiplier is useful for applications requiring more than 18-bit
precision, for example, for mantissa multiplication of precision floating-
point arithmetic applications.
Multiply Accumulate Mode
In multiply accumulate mode, the output of the multiplier stage feeds the
adder/output block which is configured as an accumulator or subtractor.
Figure 6–10 shows the DSP block configured to operate in multiply
accumulate mode.
Figure 6–10. Multiply Accumulate Mode
shiftinb shiftina
aclr[3..0]
clock[3..0]
ena[3..0]
accum_sload_upper_data (3)
accum_sload (3)
Data A
Data B
DQ
ENA
CLRN
DQ
ENA
CLRN
Q1.15
Round/
Saturate
DQ
ENA
CLRN
DQ
ENA
Accumulator
Q1.15
Round/
Saturate
DQ
ENA
CLRN
DQ
ENA
DQ
ENA
DQ
ENA
Data Out
accum_is_saturated (4)
overflow
mult_is_saturated (4)
shiftoutb shiftouta
signb (1), (2)
signa (1), (2)
mult_round (2)
mult_saturate (2)
addnsub (3)
signb (1), (3)
signa (1), (3)
accum_round (3)
accum_saturate (3)
Notes to Figure 6–10:
(1) The signa and signb signals are the same in the multiplier stage and the adder/output block.
(2) These signals are not registered or registered once to match the data path pipeline.
(3) You can send these signals through either one or two pipeline registers.
(4) These signals match the latency of the data path.
A single DSP block can implement up to two independent 18-bit
multiplier accumulators. The Quartus II software implements smaller
multiplier accumulators by tying the unused lower-order bits of the 18-bit
multiplier to ground.
The multiplier accumulator output can be up to 52-bits wide to account
for a 36-bit multiplier result with 16-bits of accumulation. In this mode,
the DSP block uses output registers and the accum_sload and overflow
Altera Corporation
January 2008
6–25
Stratix II Device Handbook, Volume 2