EP2S90F1020C5 Datasheet, PDF (511/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
Using Corner and Center Fast PLLs
■ The corner and center fast PLLs can be used as long as the channels
driven by separate fast PLLs do not have their transmitter or receiver
channels interleaved. Figure 5–25 shows illegal placement of
differential channels when using corner and center fast PLLs.
■ If one fast PLL is driving transmitter channels only, and the other fast
PLL drives receiver channels only, the channels driven by those fast
PLLs can overlap each other.
■ Center fast PLLs can be used for both transmitter and receiver
channels.
Figure 5–25. Illegal Placement of Interlaced Duplex Channels in an I/O Bank
Fast PLL
Ref CLK
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Corner PLL
Ref CLK
Duplex Channel Driven
by Center PLL
Duplex Channel Driven
by Corner PLL
Interleaved Duplex
Channel is Not Allowed
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Ref CLK
Fast PLL
Ref CLK
Center PLL
Board Design
Considerations
f
This section explains how to achieve the optimal performance from the
Stratix II and Stratix II GX high-speed I/O block and ensure first-time
success in implementing a functional design with optimal signal quality.
For more information on board layout recommendations and I/O pin
terminations, refer to AN 224: High-Speed Board Layout Guidelines.
Altera Corporation
January 2008
5–27
Stratix II Device Handbook, Volume 2