EP2S90F1020C5 Datasheet, PDF (643/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Configuring Stratix II and Stratix II GX Devices
Figure 7–37 shows JTAG configuration of a Stratix II or Stratix II GX
device with a microprocessor.
Figure 7–37. JTAG Configuration of a Single Device Using a Microprocessor
Memory
ADDR
DATA
Microprocessor
Stratix II Device
VCC (1)
VCC (1)
1 kΩ
1 kΩ
VCC
TRST
TDI
TCK
TMS
TDO
nSTATUS
CONF_DONE
nCONFIG
MSEL[3..0]
nCEO
(3) nCE
(2)
(2)
N.C.
GND
Notes to Figure 7–37:
(1) The pull-up resistor should be connected to a supply that provides an acceptable
input signal for all devices in the chain. V_CC should be high enough to meet the V_IH
specification of the I/O on the device.
(2) The nCONFIG, MSEL[3..0] pins should be connected to support a non-JTAG
configuration scheme. If only JTAG configuration is used, connect nCONFIG to
V_CC, and MSEL[3..0] to ground. Pull DCLK either high or low, whichever is
convenient on your board.
(3) nCE must be connected to GND or driven low for successful JTAG configuration.
f
Jam STAPL
Jam STAPL, JEDEC standard JESD-71, is a standard file format for
in-system programmability (ISP) purposes. Jam STAPL supports
programming or configuration of programmable devices and testing of
electronic systems, using the IEEE 1149.1 JTAG interface. Jam STAPL is a
freely licensed open standard.
The Jam Player provides an interface for manipulating the IEEE Std.
1149.1 JTAG TAP state machine.
For more information on JTAG and Jam STAPL in embedded
environments, refer to AN 122: Using Jam STAPL for ISP & ICR via an
Embedded Processor. To download the jam player, visit the Altera web site
at www.altera.com.
Altera Corporation
January 2008
7–91
Stratix II Device Handbook, Volume 2