EP2S90F1020C5 Datasheet, PDF (168/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Timing Model
Figure 5–3. Input Register Setup & Hold Timing Diagram
Input Data Delay
Input Clock Delay
micro t_SU
micro t_H
For output timing, different I/O standards require different baseline
loading techniques for reporting timing delays. Altera characterizes
timing delays with the required termination for each I/O standard and
with 0 pF (except for PCI and PCI-X which use 10 pF) loading and the
timing is specified up to the output pin of the FPGA device. The
Quartus II software calculates the I/O timing for each I/O standard with
a default baseline loading as specified by the I/O standards.
The following measurements are made during device characterization.
Altera measures clock-to-output delays (t_CO) at worst-case process,
minimum voltage, and maximum temperature (PVT) for default loading
conditions shown in Table 5–34. Use the following equations to calculate
clock pin to output pin timing for Stratix II devices.
t_CO from clock pin to I/O pin = delay from clock pad to I/O output
register + IOE output register clock-to-output delay + delay from
output register to output pin + I/O output delay
t_xz/t_zx from clock pin to I/O pin = delay from clock pad to I/O
output register + IOE output register clock-to-output delay + delay
from output register to output pin + I/O output delay + output
enable pin delay
Simulation using IBIS models is required to determine the delays on the
PCB traces in addition to the output pin delay timing reported by the
Quartus II software and the timing model in the device handbook.
1. Simulate the output driver of choice into the generalized test setup,
using values from Table 5–34.
2. Record the time to V_MEAS.
3. Simulate the output driver of choice into the actual PCB trace and
load, using the appropriate IBIS model or capacitance value to
represent the load.
5–22
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011