EP2S90F1020C5 Datasheet, PDF (433/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

External Memory Interfaces in Stratix II and Stratix II GX Devices
Figure 3–17. DQ Captures with Non-Inverted and Inverted Shifted DQS
DQ & DQS Signals
DQ at the pin
D_{n − 1}
D_n
DQS at the pin
Shifted DQS Signal is Not Inverted
DQS shifted
by 90˚
Output of register A₁
(dataout_h)
Output of register B₁
Output of latch C₁
(dataout_l)
Shifted DQS Signal is Inverted
DQS inverted and
shifted by 90˚
Output of register A₁
(dataout_h)
Output of register B₁
Output of latch C₁
(dataout_l)
D_{n − 1}
D_{n − 2}
D_n
D_{n − 2}
D_{n − 2}
D_{n − 1}
D_{n − 3}
D_n
D_{n − 1}
Altera Corporation
January 2008
3–37
Stratix II Device Handbook, Volume 2