EP2S90F1020C5 Datasheet, PDF (298/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Advanced Features
the primary to the secondary clock for PLL reference. The design sends
out the clk0_bad, clk1_bad, and the clk_loss signals from the PLL
to implement a custom switchover circuit.
Figure 1–17. Automatic Clock Switchover Circuit Block Diagram
clksw
Clock
Sense
Switch-Over
State
Machine
clk0_bad
clk0_bad
Activeclock
clkloss
inclk0
inclk1
muxout
n Counter
refclk
PFD
clkswitch
Provides manual
switchover support.
fbclk
There are two possible ways to use the clock switchover feature.
■ Use the switchover circuitry for switching from a primary to
secondary input of the same frequency. For example, in applications
that require a redundant clock with the same frequency as the
primary clock, the switchover state machine generates a signal that
controls the multiplexer select input shown on the bottom of
Figure 1–17. In this case, the secondary clock becomes the reference
clock for the PLL. This automatic switchover feature only works for
switching from the primary to secondary clock.
■ Use the CLKSWITCH input for user- or system-controlled switch
conditions. This is possible for same-frequency switchover or to
switch between inputs of different frequencies. For example, if
inclk0 is 66 MHz and inclk1 is 100 MHz, you must control the
switchover because the automatic clock-sense circuitry cannot
monitor primary and secondary clock frequencies with a frequency
difference of more than 20%. This feature is useful when clock
sources can originate from multiple cards on the backplane,
requiring a system-controlled switchover between frequencies of
operation. You should choose the secondary clock frequency so the
1–34
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009