EP2S90F1020C5 Datasheet, PDF (352/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Clock Control Block
Figure 1–53. Regional Clock Control Block
PLL Counter
Outputs (3)
CLKp CLKn
Pin Pin (2)
2
Internal
Logic
Static Clock Select (1)
Enable/
Disable
Internal
Logic
RCLK
Notes to Figure 1–53:
(1) These clock select signals can only be dynamically controlled through a
configuration file and cannot be dynamically controlled during user-mode
operation.
(2) Only the CLKn pins on the top and bottom for the device feed to regional clock
select blocks.
For the global clock select block, the clock source selection can be
controlled either statically or dynamically. You have the option to
statically select the clock source in configuration file generated by the
Quartus II software, or you can control the selection dynamically by
using internal logic to drive the multiplexer select inputs. When selecting
statically, the clock source can be set to any of the inputs to the select
multiplexer. When selecting the clock source dynamically, you can either
select two PLL outputs (such as CLK0 or CLK1), or a combination of clock
pins or PLL outputs.
When using the altclkctrl megafunction to implement clock source
(dynamics) selection, the inputs from the clock pins feed the
inclock[0..1] ports of the multiplexer, while the PLL outputs feed the
inclock[2..3] ports. You can choose from among these inputs using
the CLKSELECT[1..0] signal.
For the regional clock select block, the clock source selection can only be
controlled statically using configuration bits. Any of the inputs to the
clock select multiplexer can be set as the clock source.
The Stratix II and Stratix II GX clock networks can be disabled (powered
down) by both static and dynamic approaches. When a clock net is
powered down, all the logic fed by the clock net is in an off-state, thereby
reducing the overall power consumption of the device.
1–88
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009