HD64F2357VF13 Datasheet, PDF (973/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

TCNT—Timer Counter
H'FFBC (W), H'FFBD (R)
WDT
Bit
:7
6
5
4
3
2
1
0
Initial value : 0
Read/Write : R/W
0
0
R/W R/W
0
0
0
R/W R/W R/W
0
0
R/W R/W
TCNT is an 8-bit readable/writable* up-counter.
Note: * TCNT is write-protected by a password to prevent accidental overwriting.
For details see section 13.2.4, Notes on Register Access.
RSTCSR—Reset Control/Status Register
H'FFBE (W) , H'FFBF (R)
WDT
Bit
:
7
6
5
4
3
2
1
0
WOVF RSTE RSTS
—
—
—
—
—
Initial value :
0
0
0
1
1
1
1
1
Read/Write : _{R/(W)* R/W R/W}
—
—
—
—
—
Reset Select
0 Power-on reset
1 Manual reset*
Note: * Manual reset is not supported in the H8S/2357
(F-ZTAT and masked ROM versions) or the H8S/2352,
H8S/2398, H8S/2394, H8S/2392 and H8S/2390.
In these models, only 0 should be written to this bit.
Reset Enable
0 Reset signal is not generated if TCNT overflows*
1 Reset signal is generated if TCNT overflows
Note: * The modules H8S/2357 Group are not reset, but TCNT and
TCSR in WDT are reset.
Watchdog Timer Overflow Flag
0 [Clearing condition]
Cleared by reading RSTCSR when WOVF = 1, then writing 0 to WOVF
1 [Setting condition]
Set when TCNT overflows (changed from H'FF to H'00) during
watchdog timer operation
Note: * Can only be written with 0 for flag clearing.
The method for writing to RSTCSR is different from that for general registers to prevent
accidental overwriting. For details see section 13.2.4, Notes on Register Access.
Rev.6.00 Oct.28.2004 page 943 of 1016
REJ09B0138-0600H