HD64F2357VF13 Datasheet, PDF (234/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

7.5.5 Single Address Mode
Single address mode can only be specified for channel B. This mode can be specified by setting the SAE bit in DMABCR
to 1 in short address mode.
One address is specified by MAR, and the other is set automatically to the data transfer acknowledge pin (DACK). The
transfer direction can be specified by the DTDIR in DMACR.
Table 7-9 summarizes register functions in single address mode.
Table 7-9 Register Functions in Single Address Mode
Register
23
MAR
DACK pin
15
ETCR
Legend:
MAR: Memory address register
IOAR: I/O address register
ETCR: Transfer count register
DTDIR:Data transfer direction bit
DACK: Data transfer acknowledge
Function
DTDIR = 0 DTDIR = 1 Initial Setting
Operation
0 Source
address
register
Destination Start address of *
address transfer destination
register or transfer source
Write
strobe
Read
strobe
(Set automatically Strobe for external
by SAE bit; IOAR is device
invalid)
0 Transfer counter
Number of transfers *
Note: * See the operation descriptions in sections 7.5.2, Sequential Mode, 7.5.3, Idle Mode, and 7.5.4, Repeat Mode.
MAR specifies the start address of the transfer source or transfer destination as 24 bits.
IOAR is invalid; in its place the strobe for external devices (DACK) is output.
Rev.6.00 Oct.28.2004 page 204 of 1016
REJ09B0138-0600H