HD64F2357VF13 Datasheet, PDF (409/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

10.4.4 Buffer Operation
Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers.
Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare
match register.
Table 10-5 shows the register combinations used in buffer operation.
Table 10-5 Register Combinations in Buffer Operation
Channel
0
3
Timer General Register
TGR0A
TGR0B
TGR3A
TGR3B
Buffer Register
TGR0C
TGR0D
TGR3C
TGR3D
• When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer
general register.
This operation is illustrated in figure 10-16.
Compare match signal
Buffer register
Timer general
register
Comparator
TCNT
Figure 10-16 Compare Match Buffer Operation
• When TGR is an input capture register
When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general
register is transferred to the buffer register.
This operation is illustrated in figure 10-17.
Input capture
signal
Buffer register
Timer general
register
TCNT
Figure 10-17 Input Capture Buffer Operation
Rev.6.00 Oct.28.2004 page 379 of 1016
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