HD64F2357VF13 Datasheet, PDF (504/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

The MPIE bit setting is invalid in clocked synchronous mode or when the MP bit is cleared to 0.
Bit 3
MPIE
Description
0
Multiprocessor interrupts disabled (normal reception performed)
(Initial value)
[Clearing conditions]
• When the MPIE bit is cleared to 0
• When MPB= 1 data is received
1
Multiprocessor interrupts enabled*
Receive data full interrupt (RXI) requests, receive error interrupt (ERI) requests, and
setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the
multiprocessor bit set to 1 is received.
Note: * When receive data including MPB = 0 is received, receive data transfer from RSR to RDR, receive error detection,
and setting of the RDRF, FER, and ORER flags in SSR, is not performed. When receive data including MPB = 1 is
received, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI
interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled.
Bit 2—Transmit End Interrupt Enable (TEIE): Enables or disables transmit end interrupt (TEI) request generation
when there is no valid transmit data in TDR in MSB data transmission.
Bit 2
TEIE
Description
0
Transmit end interrupt (TEI) request disabled*
(Initial value)
1
Transmit end interrupt (TEI) request enabled*
Note: * TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0 and clearing the
TEND flag to 0, or clearing the TEIE bit to 0.
Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or
disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin
functions as an I/O port, the serial clock output pin, or the serial clock input pin.
The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in asynchronous mode. The
CKE0 bit setting is invalid in clocked synchronous mode, and in the case of external clock operation (CKE1 = 1). Note
that the SCI’s operating mode must be decided using SMR before setting the CKE1 and CKE0 bits.
Rev.6.00 Oct.28.2004 page 474 of 1016
REJ09B0138-0600H