HD64F2357VF13 Datasheet, PDF (925/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

SCKCR—System Clock Control Register
H'FF3A
Clock Pulse Generator
Bit
:
7
6
5
4
PSTOP —
—
—
Initial value :
0
0
0
0
Read/Write : R/W
R/W —/(R/W) —
3
2
1
0
—
SCK2 SCK1 SCK0
0
0
0
0
—
R/W
R/W
R/W
Reserved for
H8S/2398,
H8S/2394,
H8S/2392,
and H8S/2390.
Only 0 should
be written
to this bit.
Reserved
Only 0 should be written to
this bit.
Bus Master Clock Select
0 0 0 Bus master is in high-speed mode
1 Medium-speed clock is ø/2
1 0 Medium-speed clock is ø/4
1 Medium-speed clock is ø/8
1 0 0 Medium-speed clock is ø/16
1 Medium-speed clock is ø/32
1 ——
ø Clock Output Control
PSTOP Normal Operation
0
ø output
1
Fixed high
Sleep Mode
ø output
Fixed high
Software
Standby Mode
Fixed high
Fixed high
Hardware
Standby Mode
High impedance
High impedance
MDCR—Mode Control Register
H'FF3B
Bit
:
7
6
5
4
—
—
—
—
Initial value :
1
0
0
0
Read/Write : —
—
—
—
Note: * Determined by pins MD₂ to MD₀
MCU
3
2
1
0
— MDS2 MDS1 MDS0
0
—*
—*
—*
—
R
R
R
Current mode pin operating mode
MSTPCRH — Module Stop Control Register H H'FF3C
MSTPCRL — Module Stop Control Register L H'FF3D
Power-Down State
Power-Down State
MSTPCRH
MSTPCRL
Bit
: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value : 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Specifies module stop mode
0 Module stop mode cleared
1 Module stop mode set
Rev.6.00 Oct.28.2004 page 895 of 1016
REJ09B0138-0600H