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HD64F2357VF13 Datasheet, PDF (361/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents
Pin
Selection Method and Pin Functions
PF2/LCAS/WAIT/ The pin function is switched as shown below according to the combination of
BREQO
the operating mode, and bits RMTS2 to RMTS0, LCASS, BREQOE, WAITE,
ABW5 to ABW2, and PF2DDR.
Operating
Mode
Modes 4 to 6*2
Mode 7*2
LCASS
0*1
1
—
BREQOE
—
0
1
—
WAITE
—
0
1
—
—
PF2DDR
—
0
1
—
—
0
1
Pin function
LCAS
output
pin
PF2
input
pin
PF2
output
pin
WAIT BREQO PF2
input output input
pin
pin
pin
PF2
output
pin
Note: 1. Only in DRAM space 16-bit access in modes 4 to 6 when RMTS2 to
RMTS0 = B'001 to B'011.
2. Modes 6 and 7 are provided in the on-chip ROM version only.
PF1/BACK
The pin function is switched as shown below according to the combination of
the operating mode, and bits BRLE and PF1DDR.
Operating
Mode
Modes 4 to 6*
Mode 7*
BRLE
0
1
—
PF1DDR
0
1
—
0
1
Pin function
PF1
PF1
BACK
PF1
PF1
input pin output pin output pin input pin output pin
PF0/BREQ
Note: * Modes 6 and 7 are provided in the on-chip ROM version only.
The pin function is switched as shown below according to the combination of
the operating mode, and bits BRLE and PF0DDR.
Operating
Mode
Modes 4 to 6*
Mode 7*
BRLE
0
1
—
PF0DDR
0
1
—
0
1
Pin function
PF0
PF0
BREQ
PF0
PF0
input pin output pin input pin input pin output pin
Note: * Modes 6 and 7 are provided in the on-chip ROM version only.
Rev.6.00 Oct.28.2004 page 331 of 1016
REJ09B0138-0600H