HD64F2357VF13 Datasheet, PDF (627/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Start
*1
Set SWE bit in FLMCR1
Wait (x) µs
*2
n=1
Set EBR1, EBR2
*4
Enable WDT
Set ESU bit in FLMCR2
Wait (y) µs
Set E bit in FLMCR1
Wait (z) ms
Clear E bit in FLMCR1
Wait (α) µs
Clear ESU bit in FLMCR2
Wait (β) µs
Disable WDT
Set EV bit in FLMCR1
Wait (γ) µs
*2
Start of erase
*2
Halt erase
*2
*2
*2
Set block start address to verify address
n←n+1
H'FF dummy write to verify address
Wait (ε) µs
*2
Increment
address
NG
Read verify data
Verify data = all 1?
OK
Last address of block?
OK
Clear EV bit in FLMCR1
*3
NG
Clear EV bit in FLMCR1
Wait (η) µs
*2
NG ^*5
End of
erasing of all erase
blocks?
OK
Clear SWE bit in FLMCR1
Wait (η) µs
*2
*2
NG
n ≥ N?
OK
Clear SWE bit in FLMCR1
End of erasing
Erase failure
Notes: 1. Preprogramming (setting erase block data to all 0) is not necessary.
2. The values of x, y, z, α, β, γ, ε, η, and N are shown in section 22.7.6, Flash Memory Characteristics.
3. Verify data is read in 16-bit (W) units.
4. Set only one bit in EBR1or EBR2. More than one bit cannot be set.
5. Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially.
Figure 19-20 Erase/Erase-Verify Flowchart (Single-Block Erase)
Rev.6.00 Oct.28.2004 page 597 of 1016
REJ09B0138-0600H