HD64F2357VF13 Datasheet, PDF (701/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Bits 2 to 0—System Clock Select (SCK2 to SCK0): These bits select the clock for the bus master.
Bit 2
SCK2
0
1
Bit 1
SCK1
0
1
0
1
Bit 0
SCK0
0
1
0
1
0
1
—
Description
Bus master in high-speed mode
Medium-speed clock is ø/2
Medium-speed clock is ø/4
Medium-speed clock is ø/8
Medium-speed clock is ø/16
Medium-speed clock is ø/32
—
(Initial value)
21.2.3 Module Stop Control Register (MSTPCR)
MSTPCRH
MSTPCRL
Bit
: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value : 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R/W
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR is a 16-bit readable/writable register that performs module stop mode control.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode.
Bits 15 to 0—Module Stop (MSTP 15 to MSTP 0): These bits specify module stop mode. See table 21-3 for the method
of selecting on-chip supporting modules.
Bits 15 to 0
MSTP15 to MSTP0
0
1
Description
Module stop mode cleared
Module stop mode set
Rev.6.00 Oct.28.2004 page 671 of 1016
REJ09B0138-0600H