HD64F2357VF13 Datasheet, PDF (469/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

12.2.5 Timer Control/Status Registers 0 and 1 (TCSR0, TCSR1)
TCSR0
Bit
:
Initial value :
R/W
:
7
CMFB
0
R/(W)*
6
CMFA
0
R/(W)*
5
OVF
0
R/(W)*
4
ADTE
0
R/W
3
OS3
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
0
OS0
0
R/W
TCSR1
Bit
:
7
6
5
4
CMFB CMFA OVF
—
Initial value :
0
0
0
1
R/W
: R/(W)* R/(W)* R/(W)* —
3
OS3
0
R/W
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
2
OS2
0
R/W
1
OS1
0
R/W
0
OS0
0
R/W
TCSR0 and TCSR1 are 8-bit registers that display compare match and overflow statuses, and control compare match
output.
TCSR0 is initialized to H'00, and TCSR1 to H'10, by a reset and in hardware standby mode.
Bit 7—Compare Match Flag B (CMFB): Status flag indicating whether the values of TCNT and TCORB match.
Bit 7
CMFB
0
1
Description
[Clearing conditions]
(Initial value)
• Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB
• When DTC is activated by CMIB interrupt while DISEL bit of MRB in DTC is 0
[Setting condition]
Set when TCNT matches TCORB
Bit 6—Compare Match Flag A (CMFA): Status flag indicating whether the values of TCNT and TCORA match.
Bit 6
CMFA
0
1
Description
[Clearing conditions]
(Initial value)
• Cleared by reading CMFA when CMFA = 1, then writing 0 to CMFA
• When DTC is activated by CMIA interrupt while DISEL bit of MRB in DTC is 0
[Setting condition]
Set when TCNT matches TCORA
Rev.6.00 Oct.28.2004 page 439 of 1016
REJ09B0138-0600H