HD64F2357VF13 Datasheet, PDF (456/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Example of Normal Pulse Output (Example of Five-Phase Pulse Output): Figure 11-5 shows an example in which
pulse output is used for cyclic five-phase pulse output.
TCNT value
TGRA
TCNT
Compare match
H'0000
NDRH
Time
80 C0 40 60 20 30 10 18 08 88 80 C0 40
PODRH 00 80 C0 40 60 20 30 10 18 08 88 80 C0
PO15
PO14
PO13
PO12
PO11
Figure 11-5 Normal Pulse Output Example (Five-Phase Pulse Output)
[1] Set up the TPU channel to be used as the output trigger channel so that TGRA is an output compare register and the
counter will be cleared by compare match A. Set the trigger period in TGRA and set the TGIEA bit in TIER to 1 to
enable the compare match A (TGIA) interrupt.
[2] Write H'F8 in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0 bits in PCR to select
compare match in the TPU channel set up in the previous step to be the output trigger. Write output data H'80 in
NDRH.
[3] The timer counter in the TPU channel starts. When compare match A occurs, the NDRH contents are transferred to
PODRH and output. The TGIA interrupt handling routine writes the next output data (H'C0) in NDRH.
[4] Five-phase overlapping pulse output (one or two phases active at a time) can be obtained subsequently by writing
H'40, H'60, H'20, H'30. H'10, H'18, H'08, H'88... at successive TGIA interrupts. If the DTC or DMAC is set for
activation by this interrupt, pulse output can be obtained without imposing a load on the CPU.
11.3.4 Non-Overlapping Pulse Output
Sample Setup Procedure for Non-Overlapping Pulse Output: Figure 11-6 shows a sample procedure for setting up
non-overlapping pulse output.
Rev.6.00 Oct.28.2004 page 426 of 1016
REJ09B0138-0600H