HD64F2357VF13 Datasheet, PDF (213/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

7.3.4 DMA Control Register (DMACR)
DMACR is a 16-bit readable/writable register that controls the operation of each DMAC channel. In full address mode,
DMACRA and DMACRB have different functions.
DMACR is initialized to H'0000 by a reset, and in hardware standby mode.
DMACRA
Bit
: 15
14
13
12
11
10
9
8
DMACRA : DTSZ SAID SAIDE BLKDIR BLKE
—
—
—
Initial value :
0
0
0
0
0
0
0
0
R/W
: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DMACRB
Bit
:
7
DMACRB : —
Initial value :
0
R/W
: R/W
6
5
4
DAID DAIDE
—
0
0
0
R/W
R/W
R/W
3
DTF3
0
R/W
2
DTF2
0
R/W
1
DTF1
0
R/W
0
DTF0
0
R/W
Bit 15—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time.
Bit 15
DTSZ
0
1
Description
Byte-size transfer
Word-size transfer
(Initial value)
Bit 14—Source Address Increment/Decrement (SAID)
Bit 13—Source Address Increment/Decrement Enable (SAIDE): These bits specify whether source address register
MARA is to be incremented, decremented, or left unchanged, when data transfer is performed.
Bit 14
SAID
0
1
Bit 13
SAIDE
0
1
0
1
Description
MARA is fixed
(Initial value)
MARA is incremented after a data transfer
• When DTSZ = 0, MARA is incremented by 1 after a transfer
• When DTSZ = 1, MARA is incremented by 2 after a transfer
MARA is fixed
MARA is decremented after a data transfer
• When DTSZ = 0, MARA is decremented by 1 after a transfer
• When DTSZ = 1, MARA is decremented by 2 after a transfer
Bit 12—Block Direction (BLKDIR)
Rev.6.00 Oct.28.2004 page 183 of 1016
REJ09B0138-0600H