HD64F2357VF13 Datasheet, PDF (81/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

(3) Hardware Standby Mode: A transition to hardware standby mode is made when the STBY pin goes low. In
hardware standby mode, the CPU and clock halt and all MCU operations stop. The on-chip supporting modules are reset,
but as long as a specified voltage is supplied, on-chip RAM contents are retained.
2.9 Basic Timing
2.9.1 Overview
The CPU is driven by a system clock, denoted by the symbol ø. The period from one rising edge of ø to the next is
referred to as a "state." The memory cycle or bus cycle consists of one, two, or three states. Different methods are used to
access on-chip memory, on-chip supporting modules, and the external address space.
2.9.2 On-Chip Memory (ROM, RAM)
On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and word transfer instruction.
Figure 2-14 shows the on-chip memory access cycle. Figure 2-15 shows the pin states.
ø
Internal address bus
Read
access
Internal read signal
Internal data bus
Write
access
Internal write signal
Internal data bus
Bus cycle
T1
Address
Read data
Write data
Figure 2-14 On-Chip Memory Access Cycle
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