HD64F2357VF13 Datasheet, PDF (574/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): Together with the SCAN bit, these bits select the analog input
channels.
Only set the input channel while conversion is stopped (ADST = 0).
Group
Selection
CH2
0
1
Channel Selection
CH1
CH0
0
0
1
1
0
1
0
0
1
1
0
1
Description
Single Mode (SCAN=0) Scan Mode (SCAN=1)
AN0 (Initial value)
AN0
AN1
AN0, AN1
AN2
AN0 to AN2
AN3
AN0 to AN3
AN4
AN4
AN5
AN4, AN5
AN6
AN4 to AN6
AN7
AN4 to AN7
16.2.3 A/D Control Register (ADCR)
Bit
:
7
6
5
4
3
2
1
0
TRGS1 TRGS0 —
—
—
—
—
—
Initial value :
0
0
1
1
1
1
1
1
R/W
: R/W
R/W
—
— —/(R/W)* —/(R/W)* —
—
Note: * Applies to the H8S/2398, H8S/2394, H8S/2392, and H8S/2390.
ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion operations.
ADCR is initialized to H'3F by a reset, and in standby mode or module stop mode.
Bits 7 and 6—Timer Trigger Select 1 and 0 (TRGS1, TRGS0): Select enabling or disabling of the start of A/D
conversion by a trigger signal. Only set bits TRGS1 and TRGS0 while conversion is stopped (ADST = 0).
Bit 7
TRGS1
0
1
Bit 6
TRGS0
0
1
0
1
Description
A/D conversion start by external trigger is disabled
(Initial value)
A/D conversion start by external trigger (TPU) is enabled
A/D conversion start by external trigger (8-bit timer) is enabled
A/D conversion start by external trigger pin (ADTRG) is enabled
(1) For H8S/2357 and H8S/2352
Bits 5 to 0—Reserved: They are always read as 1 and cannot be modified.
(2) For H8S/2398, H8S/2394, H8S/2392, and H8S/2390
Bits 5, 4, 1, and 0—Reserved: They are always read as 1 and cannot be modified.
Bits 3 and 2—Reserved: Should always be written with 1.
Rev.6.00 Oct.28.2004 page 544 of 1016
REJ09B0138-0600H