HD64F2357VF13 Datasheet, PDF (499/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

14.2 Register Descriptions
14.2.1 Receive Shift Register (RSR)
Bit
:
7
6
5
4
3
2
1
0
R/W : —
—
—
—
—
—
—
—
RSR is a register used to receive serial data.
The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the LSB (bit 0), and converts it
to parallel data. When one byte of data has been received, it is transferred to RDR automatically.
RSR cannot be directly read or written to by the CPU.
14.2.2 Receive Data Register (RDR)
Bit
:
7
6
5
4
3
2
1
0
Initial value :
0
0
0
0
0
0
0
0
R/W
:
R
R
R
R
R
R
R
R
RDR is a register that stores received serial data.
When the SCI has received one byte of serial data, it transfers the received serial data from RSR to RDR where it is stored,
and completes the receive operation. After this, RSR is receive-enabled.
Since RSR and RDR function as a double buffer in this way, enables continuous receive operations to be performed.
RDR is a read-only register, and cannot be written to by the CPU.
RDR is initialized to H'00 by a reset, and in standby mode or module stop mode.
14.2.3 Transmit Shift Register (TSR)
Bit
:
7
6
5
4
3
2
1
0
R/W : —
—
—
—
—
—
—
—
TSR is a register used to transmit serial data.
To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD
pin starting with the LSB (bit 0).
When transmission of one byte is completed, the next transmit data is transferred from TDR to TSR, and transmission
started, automatically. However, data transfer from TDR to TSR is not performed if the TDRE bit in SSR is set to 1.
TSR cannot be directly read or written to by the CPU.
Rev.6.00 Oct.28.2004 page 469 of 1016
REJ09B0138-0600H