HD64F2357VF13 Datasheet, PDF (131/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

5.6.2 Block Diagram
Figure 5-9 shows a block diagram of the DTC and DMAC interrupt controller.
DMAC
Interrupt
request
IRQ
interrupt
Interrupt source
On-chip _{clear signal}
supporting
module
Selection
circuit
Select
signal
Clear signal
DTCER
Control logic
DTVECR
SWDTE
clear signal
Interrupt controller
Determination of
priority
DTC activation
request vector
number
Clear signal
DTC
CPU interrupt
request vector
number
I, I2 to I0
CPU
Figure 5-9 Interrupt Control for DTC and DMAC
5.6.3 Operation
The interrupt controller has three main functions in DTC and DMAC control.
Selection of Interrupt Source: With the DMAC, the activation source is input directly to each channel. The activation
source for each DMAC channel is selected with bits DTF3 to DTF0 in DMACR. Whether the selected activation source is
to be managed by the DMAC can be selected with the DTA bit of DMABCR. When the DTA bit is set to 1, the interrupt
source constituting that DMAC activation source is not a DTC activation source or CPU interrupt source.
For interrupt sources other than interrupts managed by the DMAC, it is possible to select DTC activation request or CPU
interrupt request with the DTCE bit of DTCERA to DTCERF in the DTC.
After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the CPU in accordance with
the specification of the DISEL bit of MRB in the DTC.
When the DTC has performed the specified number of data transfers and the transfer counter value is zero, the DTCE bit
is cleared to 0 and an interrupt request is sent to the CPU after the DTC data transfer.
Determination of Priority: The DTC activation source is selected in accordance with the default priority order, and is not
affected by mask or priority levels. See section 7.6, Interrupts, and section 8.3.3, DTC Vector Table, for the respective
priorities.
With the DMAC, the activation source is input directly to each channel.
Operation Order: If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data
transfer is performed first, followed by CPU interrupt exception handling.
Rev.6.00 Oct.28.2004 page 101 of 1016
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