HD64F2357VF13 Datasheet, PDF (324/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

9.6 Port 5
9.6.1 Overview
Port 5 is a 4-bit I/O port. Port 5 pins also function as SCI I/O pins (TxD2, RxD2, and SCK2) and the A/D converter input
pin (ADTRG). Port 5 pin functions are the same in all operating modes. Figure 9-5 shows the port 5 pin configuration.
Port 5 pins
Port 5
P5₃ (I/O)/ADTRG (input)
P5₂ (I/O)/SCK2 (I/O)
P5₁ (I/O)/RxD2 (input)
P5₀ (I/O)/TxD2 (output)
Figure 9-5 Port 5 Pin Functions
9.6.2 Register Configuration
Table 9-9 shows the port 5 register configuration.
Table 9-9 Port 5 Registers
Name
Port 5 data direction register
Port 5 data register
Port 5 register
Notes: 1. Lower 16 bits of the address.
2. Value of bits 3 to 0.
Abbreviation
P5DDR
P5DR
PORT5
R/W
Initial Value*²
Address*¹
W
H'0
H'FEB4
R/W H'0
H'FF64
R
Undefined
H'FF54
Port 5 Data Direction Register (P5DDR)
Bit
:
7
6
5
4
3
2
1
0
—
—
—
— P53DDR P52DDR P51DDR P50DDR
Initial value : Undefined Undefined Undefined Undefined 0
0
0
0
R/W
:—
—
—
—
W
W
W
W
P5DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 5. Bits 7 to 4
are reserved. P5DDR cannot be read; if it is, an undefined value will be read.
Setting a P5DDR bit to 1 makes the corresponding port 5 pin an output pin, while clearing the bit to 0 makes the pin an
input pin.
P5DDR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a
manual reset*, and in software standby mode. As the SCI is initialized, the pin states are determined by the P5DDR and
P5DR specifications.
Rev.6.00 Oct.28.2004 page 294 of 1016
REJ09B0138-0600H