HD64F2357VF13 Datasheet, PDF (294/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

[1] Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 =
0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for
one block transfer by one interrupt (CHNE = 0). Set the transfer source address (H'1000) in SAR, the destination
address (H'2000) in DAR, and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB.
[2] Set the start address of the register information at the DTC vector address (H'04C0).
[3] Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated by software.
[4] Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0.
[5] Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this indicates that the write
failed. This is presumably because an interrupt occurred between steps 3 and 4 and led to a different software
activation. To activate this transfer, go back to step 3.
[6] If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred.
[7] After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear the SWDTE bit to 0
and perform other wrap-up processing.
8.4 Interrupts
An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer
for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is
generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control.
In the case of activation by software, a software activated data transfer end interrupt (SWDTEND) is generated.
When the DISEL bit is 1 and one data transfer has ended, or the specified number of transfers have ended, after data
transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is generated. The interrupt handling routine should
clear the SWDTE bit to 0.
When the DTC is activated by software, an SWDTEND interrupt is not generated during a data transfer wait or during
data transfer even if the SWDTE bit is set to 1.
8.5 Usage Notes
Module Stop: When the MSTP14 bit in MSTPCR is set to 1, the DTC clock stops, and the DTC enters the module stop
state. However, 1 cannot be written in the MSTP14 bit while the DTC is operating.
On-Chip RAM: The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the DTC
is used, the RAME bit in SYSCR must not be cleared to 0.
DMAC Transfer End Interrupt: When DTC transfer is activated by a DMAC transfer end interrupt, regardless of the
transfer counter and DISEL bit, the DMAC’s DTE bit is not subject to DTC control, and the write data has priority.
Consequently, an interrupt request may not be sent to the CPU when the DTC transfer counter reaches 0.
DTCE Bit Setting: For DTCE bit setting, read/write operations must be performed using bit-manipulation instructions
such as BSET and BCLR. For the initial setting only, however, when multiple activation sources are set at one time, it is
possible to disable interrupts and write after executing a dummy read on the relevant register.
Rev.6.00 Oct.28.2004 page 264 of 1016
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