HD64F2357VF13 Datasheet, PDF (704/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

21.5.2 Usage Notes
DMAC/DTC Module Stop: Depending on the operating status of the DMAC or DTC, the MSTP15 and MSTP14 bits
may not be set to 1. Setting of the DMAC or DTC module stop mode should be carried out only when the respective
module is not activated.
For details, refer to section 7, DMA Controller, and section 8, Data Transfer Controller.
On-Chip Supporting Module Interrupt: Relevant interrupt operations cannot be performed in module stop mode.
Consequently, if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the
CPU interrupt source or the DMAC or DTC activation source. Interrupts should therefore be disabled before entering
module stop mode.
Writing to MSTPCR: MSTPCR should only be written to by the CPU.
Rev.6.00 Oct.28.2004 page 674 of 1016
REJ09B0138-0600H