HD64F2357VF13 Datasheet, PDF (438/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Contention between Buffer Register Write and Input Capture: If the input capture signal is generated in the T₂ state of
a buffer write cycle, the buffer operation takes precedence and the write to the buffer register is not performed.
Figure 10-55 shows the timing in this case.
ø
Address
Write signal
Input capture
signal
TCNT
TGR
Buffer
register
Buffer register write cycle
T₁
T₂
Buffer register
address
N
M
N
M
Figure 10-55 Contention between Buffer Register Write and Input Capture
Contention between Overflow/Underflow and Counter Clearing: If overflow/underflow and counter clearing occur
simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence.
Figure 10-56 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is
set in TGR.
ø
TCNT input
clock
TCNT
Counter
clear signal
TGF
TCFV
H'FFFF
Prohibited
H'0000
Figure 10-56 Contention between Overflow and Counter Clearing
Rev.6.00 Oct.28.2004 page 408 of 1016
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