HD64F2357VF13 Datasheet, PDF (229/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

7.5.3 Idle Mode
Idle mode can be specified by setting the RPE bit and DTIE bit in DMACR to 1. In idle mode, one byte or word is
transferred in response to a single transfer request, and this is executed the number of times specified in ETCR.
One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in
DMACR.
Table 7-7 summarizes register functions in idle mode.
Table 7-7 Register Functions in Idle Mode
Register
23
MAR
23
15
H'FF
IOAR
15
ETCR
Legend:
MAR: Memory address register
IOAR: I/O address register
ETCR: Transfer count register
DTDIR:Data transfer direction bit
Function
DTDIR = 0 DTDIR = 1 Initial Setting
Operation
0 Source
address
register
Destination Start address of Fixed
address transfer destination
register or transfer source
0 Destination Source
address address
register register
Start address of Fixed
transfer source or
transfer destination
0 Transfer counter
Number of transfers Decremented every
transfer; transfer
ends when count
reaches H'0000
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is neither incremented nor
decremented each time a byte or word is transferred.
IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF.
Figure 7-5 illustrates operation in idle mode.
MAR
Transfer
1 byte or word transfer performed in
response to 1 transfer request
IOAR
Figure 7-5 Operation in Idle Mode
Rev.6.00 Oct.28.2004 page 199 of 1016
REJ09B0138-0600H