HD64F2357VF13 Datasheet, PDF (22/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

10.7 Usage Notes ..............................................................................................................................................................404
Section 11 Programmable Pulse Generator (PPG) ...........................................................................411
11.1 Overview................................................................................................................................................................... 411
11.1.1 Features ....................................................................................................................................................... 411
11.1.2 Block Diagram............................................................................................................................................. 412
11.1.3 Pin Configuration ........................................................................................................................................413
11.1.4 Registers ......................................................................................................................................................414
11.2 Register Descriptions................................................................................................................................................415
11.2.1 Next Data Enable Registers H and L (NDERH, NDERL)..........................................................................415
11.2.2 Output Data Registers H and L (PODRH, PODRL) ................................................................................... 416
11.2.3 Next Data Registers H and L (NDRH, NDRL)........................................................................................... 416
11.2.4 Notes on NDR Access................................................................................................................................. 416
11.2.5 PPG Output Control Register (PCR)........................................................................................................... 418
11.2.6 PPG Output Mode Register (PMR)............................................................................................................. 419
11.2.7 Port 1 Data Direction Register (P1DDR) ....................................................................................................421
11.2.8 Port 2 Data Direction Register (P2DDR) ....................................................................................................421
11.2.9 Module Stop Control Register (MSTPCR) ................................................................................................. 422
11.3 Operation ..................................................................................................................................................................423
11.3.1 Overview ..................................................................................................................................................... 423
11.3.2 Output Timing ............................................................................................................................................. 424
11.3.3 Normal Pulse Output ................................................................................................................................... 425
11.3.4 Non-Overlapping Pulse Output ................................................................................................................... 426
11.3.5 Inverted Pulse Output ..................................................................................................................................429
11.3.6 Pulse Output Triggered by Input Capture ................................................................................................... 430
11.4 Usage Notes ..............................................................................................................................................................431
Section 12 8-Bit Timers....................................................................................................................433
12.1 Overview................................................................................................................................................................... 433
12.1.1 Features ....................................................................................................................................................... 433
12.1.2 Block Diagram............................................................................................................................................. 434
12.1.3 Pin Configuration ........................................................................................................................................435
12.1.4 Register Configuration ................................................................................................................................435
12.2 Register Descriptions................................................................................................................................................436
12.2.1 Timer Counters 0 and 1 (TCNT0, TCNT1)................................................................................................. 436
12.2.2 Time Constant Registers A0 and A1 (TCORA0, TCORA1) ......................................................................436
12.2.3 Time Constant Registers B0 and B1 (TCORB0, TCORB1)....................................................................... 437
12.2.4 Time Control Registers 0 and 1 (TCR0, TCR1) ......................................................................................... 437
12.2.5 Timer Control/Status Registers 0 and 1 (TCSR0, TCSR1)......................................................................... 439
12.2.6 Module Stop Control Register (MSTPCR) ................................................................................................. 441
12.3 Operation ..................................................................................................................................................................442
12.3.1 TCNT Incrementation Timing..................................................................................................................... 442
12.3.2 Compare Match Timing ..............................................................................................................................443
12.3.3 Timing of External RESET on TCNT......................................................................................................... 444
12.3.4 Timing of Overflow Flag (OVF) Setting..................................................................................................... 444
12.3.5 Operation with Cascaded Connection ......................................................................................................... 445
12.4 Interrupts................................................................................................................................................................... 446
12.4.1 Interrupt Sources and DTC Activation........................................................................................................446
12.4.2 A/D Converter Activation ........................................................................................................................... 446
12.5 Sample Application ..................................................................................................................................................447
12.6 Usage Notes ..............................................................................................................................................................448
12.6.1 Contention between TCNT Write and Clear............................................................................................... 448
Rev.6.00 Oct.28.2004 page xvi of xxiv
REJ09B0138-0600H